(1) Field of the Invention
This invention relates to phase detector in a phase-locked loop, in particular to the charge pump of the phase comparator.
(2) Brief Description of Related Art
FIG. 1 shows a commonly used basic phase-locked loop (PLL) for a frequency synthesizer. A voltage controlled oscillator (VCO) generates a frequency to compare with a reference frequency in a phase comparator. The output of the phase comparator is used to feed a phase detector. In frequency synthesizers, a widely used method for phase detection is to use a charge pump after a phase comparator to derive a DC voltage for controlling the voltage-controlled oscillator (VCO). The charge pump charges a capacitor when the phase comparator output is UP, and discharges the capacitor when the phase comparator output is DOWN. The DC voltage changes the frequency of the VCO until the VCO generates a frequency, which is locked in phase with a reference frequency. The type of phase detector used in the design is known as “Three-state Phase Detector”. The three states of the output are: “high”, “low” and “high impedance”. In this type of phase detector, when both outputs of the phase comparator are “high”, the comparator resets both of its outputs to “low” state and turns off the sourcing and sinking currents of the charge pump. When this happens, the output of the charge pump is in the so-called “high impedance state”. The loop filter in the frequency synthesizer is charged or discharged by the charge pump to increase or decrease the control voltage for the VCO. The design has two problems: First, the VCO can change phase without producing a significant phase comparator output to activate the charging and discharging mechanism. Second, there is a time delay between the time phase comparator sending an output signal and the time the charge pump completely respond to the signal and turn on or off the output currents accordingly. Conventional design is to add a delay to the reset signal, but the added delay cannot track with the charge pump, thus causing the phase detector to reset the charge pump to the high impedance state too soon or too late. If resetting the charge pump too soon, a phenomenon known as “dead band” (or “dead zone”) will occur. Such an arrangement can have a dead band range in which the VCO can change phase without producing a significant phase comparator output to activate the charging and discharging mechanism. Then the VCO can fluctuate within the dead band and reduce the spectral purity of the oscillator. If resetting the charge pump too late then both the sourcing and sinking currents will exist for an excessively long time and produce no useful output current. This is because the “net” charge pump current depends on the matching of sourcing and sinking currents. For an ideal charge pump, the sourcing and sinking currents mismatch is zero percent which implies the charge pump generates no output current when both the sourcing and sinking currents are conducting at full swings. Under such situation, the thermal and shot noises generated in the sourcing and sinking devices in the charge pump will increase the VCO phase noise.
FIG. 2 shows a prior art charge pump phase detector block diagram. When the sourcing input signals Vsource is high and the sinking signal Vsink is low, the output signal S1 at Q of flip-flop F1 fed from Vsource is up, causing the output of the inverter INV1 to go low, turning on the p-channel output MOSFET M3 toggle switch and pulling up the output capacitor (not shown). Conversely, when the input signal Vsource is high, the output signal S2 at Q of flip-lop F2 goes high, causing the output of inverter INV3 to be low, the output of the inverter INV4 to be high, turning on the n-channel MOSFET M1 of the complementary toggle switch and pulling down the output capacitor. When both the UP signal Slat the output of flip-flop F1 and the DOWN signal S2 at the output of flip-flop F2 are high, a RESET signal is generated by an AND gate AND1 with inputs from S1, S2 and an output fed through a chain of inverters 13 to reset the flip-flop F1 and flip-flop F2 to set both Q outputs to be low, thereby turning off both M1 and M3 to set the output of the charge pump at the high impedance state. The function of the delay chain of inverters 13 is to compensate for the delays in the output MOSFETs M1 and M3, so that the output of the charge pump is not untimely turned off. However, since the delay chain does not track the “real” delay in the charge, the reset signal may by too early or too late. If the reset signal comes out too early, the charge pump shuts down (i.e. in the high impedance state) before the sourcing or sinking current reach its desired DC current levels. If this happens, the charge performs poorly and the phase-locked loop may degrade its performance or cause instability. If the reset signal appears too late, the can be a significantly long period of time that both the sourcing and sinking currents exist. If this happens, the sourcing and sinking currents cancel each other and result in nearly “zero” charge output current and degrade the PLL performance. In this FIG. 2, the inverter INV1 is used to invert the S1 signal for driving the PMOS M3. The inverters INV3 and INV4 are used to introduce some delay for S2 signal to drive the faster NMOS M1.